The present invention relates generally to semiconductor processing technology, and more particularly to a method for improving threshold voltage stability of a metal-oxide-semiconductor (MOS) device.
Memory devices often play an important role in modern electronic systems. One of the most widely used memory devices is the random access memory (RAM), such as static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM is a type of RAM that holds data until the values of the data are either overwritten or the power supplied thereto is taken away. This is opposed to DRAM, which allows the data to exit by the cells discharging every few milliseconds unless it is refreshed. The major layout areas of a SRAM chip are the memory cell area, logic circuit area, and input/output (I/O) circuit area. A SRAM cell is typically composed of four or six MOS devices. The SRAM cell needs not to be refreshed, and is therefore very fast, with access times in a range between 0.2 and 100 nano-seconds.
As integrated circuit (IC) chips continue to scale down, the threshold voltage stability of MOS devices in an SRAM cell becomes a concern of reliability. Conventionally, an extra ion implantation process is used to increase the dopant density in wells of the MOS devices for compensating the dopants diffused out of the channel region thereof during thermal processes. However, this extra implantation process can have adverse effects, such as higher junction capacitance, and channel dopant fluctuation, on the MOS devices in the SRAM cell. These adverse effects may cause instability of the threshold voltages of the MOS devices.
Therefore, desirable in the art of semiconductor processing technology are methods for improving the threshold voltage stability of the MOS devices.